The invention relates to microprogram controlled computers or data processing systems. These computers use a minimum of hardware controls. The controls of a microprogram controlled computer are mainly data gates that route data into and out of registers, counters, adders, and so on. In this system, one instruction (program instruction, microcode, microinstruction or control word) provides the data gates and controls for one machine cycle. A new instruction is read out of control storage during each machine (CPU or system) cycle.
Each instruction is segmented into a number of control fields. Each control field activates a specific hardware control in the system.
One of these control fields pertains to (and may at least partially define) the address of the next program instruction. In branching situations, the control field of the current instruction is used, in combination with other data, to form or define the address of the next instruction. In this case, the branch address is dependent upon said other data.
The present invention relates to program branching that can occur when a left to right instruction is being executed, where the branch address is defined, in accordance with the invention, by two data elements, namely, (1) the length of the data operands involved in the left to right instruction, and (2) the alignment of that portion of the operands presently in two or more registers that interface with main data storage.
Conditional branching is well known in the data processing art. Some examples are as follows.
U.S. Pat. No. 3,570,006 describes an arrangement for multiple branching wherein a plurality of predefined branch addresses are pre-established in a plurality of branch address registers. As the program executes, branch conditions are tested. When a test condition is satisfied, this fact is stored in a particular one of a plurality of flip-flops. Scanning of the flip-flops enables the predefined program branch addresses to be used to address memory.
U.S. Pat. No. 3,979,725 discloses an arrangement for multi-way program branching wherein a branch address is in part based upon the contents of the data in a register. More specifically, sixteen read-only PROMs are arranged in four groups of four PROMs. Two bits of a 16-bit instruction currently being executed are used to address the PROMs. Two other bits of the instruction are used in combination with the output of the addressed PROM to address the next instruction when a branch condition occurs. The output of the addressed PROMs is a function of the data in a register.
U.S. Pat. No. 4,430,706 discloses an arrangement for loading the next program address, or alternatively a branch address, based upon whether or not the program branched the last time the program was executed.
A related portion of the prior IBM System 38 data processing system is shown in FIG. 1. This prior system provides a form of branching when executing left to right instructions.
This prior system is described in the IBM System/38 Theory-Maintenance manual SY31-0649-2, incorporated herein by reference.
The System 38 processing system is typical of systems that process strings of multi-byte data that resides in consecutive byte aligned memory locations in main memory storage 10.
When this prior data processing system executes a left to right instruction, a 4-way microcode branch is possible, based upon (1) the byte length of the portion of data operand that remains to be processed, and (2) alignment of the portion of the operands (which may be the entire operands) in two registers SA and SB that interface to main storage 10. The byte length parameter is contained in 8-bit register L. The alignment parameter for each of the registers SA and SB is contained in 2-bit registers A and B, respectively.
The System 38's architecture supports a set of left to right instructions that process data that is stored in main memory 10. As shown in FIG. 1, memory 10 is one word (i.e. four bytes or 32 bits) wide. Data in memory 10 is processed from a low memory address, such as 11, toward a higher memory address, such as 12, when executing a left to right instruction.
Examples of System 38 left to right instructions are; Move Characters (MVC), Compare Logical Characters (CLC), And Character (NC), Or Character (OC), Exclusive Or Character (XC), Move Byte Immediate And Propagate (MVBIP), Move Character Long (MVCL), and Compare Logical Characters Long (CLCL). Instructions of the left to right type are frequently used by a programmer.
A limitation of this prior system is that in general it can process only one byte of data for each machine cycle. Two bytes, or four bytes for move instructions, can be processed simultaneously if the data alignment and length permit, but additional machine cycles and microcode are required to detect and exploit this capability, thus limiting the usefulness of doing so.
While the data bus of the System 38 is 4 bytes wide, its ALU is only 2 bytes wide and can process two bytes only when the data is halfword aligned. Thus, for those left to right instructions that utilize the ALU, generally only one operand byte is processed per machine cycle. However, based upon the content of the length register and one of the pointer registers (i.e. not both pointer registers as in the present invention), a maximum of two operand bytes are sometimes processed. However, System 38 is not capable of handling this larger quantity of data in one machine cycle, additional cycles being required to determine that the favorable combination of length and alignments exists.
In addition, for those left to right instructions that do not utilize the ALU while executing the instruction, the System 38 is capable of processing up to 4 operand bytes. Again this operation is based upon the content of the length register and only one of the pointer registers, and the system is not capable of handling this quantity of data in one machine cycle, additional cycles being required to determine that the favorable combination of length and alignments exists.
An important distinction of the present invention is that its MBR branch feature processes the maximum, variable, byte-quantity of operand that the machine's architecture will allow, and that this byte-quantity of operand is processed in only one machine cycle.
In each of the System 38's left to right instructions, the instruction contains (1) the address in main memory 10 where the first byte of the operand(s) can be found, (2) the byte length of the operand(s) to be fetched from memory 10, and (3) a pointer that points to the first byte of the operand(s) within the full data word that is stored at the identified address (i.e. the byte boundary 13, 14, 15 or 16 at which the operand(s) begins in the memory location that is addressed in memory 10).
The byte length of an operand may be of any integer count, up to a maximum length of 256 bytes. The operand(s) that is so defined by the instruction may exist in main memory 10 at any address, and with its first byte aligned on any of the byte boundaries 13, 14, 15 or 16 (i.e. the first byte of an operand may begin at any address such as 11 or 12, and at any of the byte boundaries within the addressed full word of memory 10). Boundary 13 is called a full word (FW) boundary, whereas boundary 15 is called a half word (HW) boundary.
The System 38 main data bus (not shown) is 4 bytes wide.
Main storage interface registers SA and SB are both 32 bits (four bytes or a FW) wide. Each of the registers SA and SB is provided with a 2-bit pointer register A and B, respectively. As shown in FIG. 1, when register A contains "00" register A points to byte 0 in register SA, when register A contains "01" it points to byte 1 in register SA, etc. This same relationship exists between register SB and pointer B.
As data is processed, one byte per cycle, registers A and B are incremented by "1" for each cycle, and register L is decremented by "1" for each cycle.
When the pointer register corresponding to one (or both) of the registers SA or SB reaches the count "11" (and assuming the 8-bit L register is not "00000000"), it is an indication that the FW content of that register must be stored, and/or that the FW content of the next higher address of memory 10 must be fetched and loaded into that register.
As described beginning at page 05-070 of the above mentioned manual, part of the data contained in a microinstruction is used to create part of the control storage address for the next microinstruction. In the case of a left to right instruction, this next microinstruction may be one of four possible microinstructions.
Each System 38 left to right microinstruction includes a field called "next address". This field, in combination with conditions such as the state of pointer registers A and B and length register L (FIG. 1), provides the address of the next microinstruction. In this arrangement, the 4-way left to right instruction branch is controlled by the state of registers A, B and L at the beginning of the cycle.
The construction and arrangement of the System 38 is such that a microinstruction can be executed in the same cycle in which the above mentioned registers A, B and L are altered and the address of the next microinstruction is determined. In addition, a register SA or SB can be used as both a source and a destination in the same cycle. Thus, a cycle is not skipped in order to accomplish these functions.
The address of the next instruction is generated early in the cycle of the currently executing instruction. This allows accessing of the next instruction to begin as soon as possible in the current cycle.
As mentioned, register L is initially loaded with the byte length of the operand(s) to be loaded from memory 10 and to be operated upon by the left to right instruction. This byte length is contained in the left to right instruction itself. As previously stated, this length parameter may be as long as 256 bytes. The length value in the L register is biased by 1, such that a value of 0 represents a length of 1.
As bytes of the operand are processed by the left to right instruction, the content of register L is decremented, once for each byte that is processed. When the content of register L becomes zero, or "00000000" at the start of a microinstruction, it is an indication that the microinstruction processed the last byte of the operand, and that the left to right instruction has been completed. L=0 generally indicates that one byte remains. When a byte is processed and L was 0 at the beginning of the cycle, it is an indication that all bytes have been processed.
More specifically, a test of the L register in which the presence of the state "00000000" is detected causes an address bit "1" to be generated as a bit 13 of the next microinstruction's address.
The two above mentioned test bits are assembled into a 14-bit address (i.e. bits 0 through 13) whose bit 12 is generated by testing registers A and B, and whose bit 13 is generated by testing the L register. The four possible states of these two address bits are "00", "01", "10" or "11". These four states determine which of the four possible microcode branches will occur.
In summary, when these two bits of the "next address" are "11" (signifying that the last byte of register SA/SB has been accessed, and that the last operand byte has been processed), or "01" (signifying that the last byte of register SA/SB has not been processed, but that the last operand byte has been processed), the end of the left to right instruction is indicated, and the next program instruction is fetched.
When the content of these two address bits is "00" (signifying that the last byte of register SA/SB has not been processed, and that the last byte of the operand has not been processed), the next byte in register SA/SB is processed.
When the content of these two address bits is "10" (signifying that the last byte of register SA/SB has been processed, but that bytes of the operand remain to be processed), the FW data content at the next higher address of memory 10 is fetched/stored to/from the registers SA/SB. In some cases, an additional cycle is required to determine whether to fetch and/or store.
While the prior systems, such as System 38, are satisfactory, the present invention provides a more efficient 16-way branch, providing more efficient use of processor hardware when executing left to right microcode instructions, thereby decreasing the number of processor cycles required to execute left to right instructions.
An important distinction between the prior System 38 and the present invention is that the length register L of the System 38 was usually used only to determine if a portion of the operand remained to be processed, i.e. except for a branch indicating that an entire word remained to be processed, the number of bytes remaining to be processed were not used as a branch parameter in System 38.
The branches available on system 38 do not allow the combination of remaining length and operand alignments to be analyzed in a single cycle such that the optimum number of bytes could be processed in the following cycle.
In the present invention, on the other hand, the amount of the operand to be processed is critical to branching. Namely, the number of bytes to be processed is determined, and branching occurs based upon the amount of operand that remains.
In this way, the present invention uses the system's dataflow paths most efficiently for the particular operand length that remains.